Korea, Eugene Investment & Securities: On the NVIDIA Rubin Ultra HBM despec NVIDIA appears to be discussing a plan to configure the main version of Rubin Ultra with a 2 die structure, HBM4 8Hi, and 8 stacks, and to add an HBM4E 8Hi version at a later point. Assuming NVIDIA's 2027 CoWoS capacity allocation is 1,200k, NVIDIA's accelerator output is estimated at 9.9M units and Rubin Ultra output at 1.6M units. If Rubin Ultra shifts from HBM4E 12Hi 384GB to HBM4 8Hi 192GB, NVIDIA's 2027 HBM demand would be revised down by roughly 10%, from 24.1bn Gb to 21.6bn Gb, and total HBM demand could decline by about 4%. Of course, this assumption does not reflect the possibility of a further expansion in accelerator output. That said, we judge this despec to be a strategy for producing more accelerators out of a limited pool of HBM bits, as the increase in HBM supply from DRAM makers has failed to keep pace with the speed of TSMC's front end and back end capacity expansion. DRAM makers find it difficult to expand HBM capacity flexibly because of the extreme shortage in commodity DRAM. With consumer set makers in smartphones and PCs experiencing production disruptions due to memory shortages, it is also not easy for memory makers to cut allocations to these customers any further.

Korea, Eugene Investment & Securities: On the NVIDIA Rubin Ultra HBM despec NVIDIA appears to be discussing a plan to configure the main version of Rubin Ultra with a 2 die structure, HBM4 8Hi, and 8 stacks, and to add an HBM4E 8Hi version at a later point. Assuming NVIDIA's 2027 CoWoS capacity allocation is 1,200k, NVIDIA's accelerator output is estimated at 9.9M units and Rubin Ultra output at 1.6M units. If Rubin Ultra shifts from HBM4E 12Hi 384GB to HBM4 8Hi 192GB, NVIDIA's 2027 HBM demand would be revised down by roughly 10%, from 24.1bn Gb to 21.6bn Gb, and total HBM demand could decline by about 4%. Of course, this assumption does not reflect the possibility of a further expansion in accelerator output. That said, we judge this despec to be a strategy for producing more accelerators out of a limited pool of HBM bits, as the increase in HBM supply from DRAM makers has failed to keep pace with the speed of TSMC's front end and back end capacity expansion. DRAM makers find it difficult to expand HBM capacity flexibly because of the extreme shortage in commodity DRAM. With consumer set makers in smartphones and PCs experiencing production disruptions due to memory shortages, it is also not easy for memory makers to cut allocations to these customers any further.

Source:https://x.com/jukan05/status/2084428229763604899