The Race Toward Autonomous Chip Design!! Anthropic is reportedly using Claude frontier models for chip design... +OpenAI and Broadcom got Jalapeneo from RTL to tapeout in just 9 months, using AI to speed up the process. OpenAI is also working with Synopsys on AI for EDA. I'm curious about a few things with Anthropic's approach: 1. To what degree is Claude doing the design for Anthropic? Is it just RTL generation and verification or does it also include synthesis, place and route, timing closure etc. until finally the GDSII file is written out? 2. Who's doing the physical implementation and signoff? OpenAI worked with Broadcom on Jalapeño, so is Anthropic planning something similar, or will they handle the entire flow in-house? 3. Are they designing just the accelerator, or the whole system, including memory, interconnects, packaging and software? 4. How much of the design process is being automated? Are agents running the tools, analyzing results, and making decisions to design the chip, or is most of the work still being done by engineers? I've previously written about how chip design is essentially a massive search problem. While being able to explore thousands of designs is great, it's not particularly useful if it takes several months to verify, optimize for PPA and then get ready for fabrication. Now imagine getting that 9-month RTL-to-tapeout cycle down to 2–3 months? Or less... What if we could try out many more architectures? There are many custom chips today that are just not worth building because of the cost. Even though fabrication and silicon validation take time, there's plenty of room for improvement in the time before tapeout. In terms of EDA, I don't think the underlying tools or signoff requirements are going away, but engineers might end up using them in very different ways. In a few years, a small team of engineers with the right PDKs/IP, AI tools to explore the search space, and a foundry budget could design and tape out chips that today would take much larger design teams. Are we approaching the end of painfully slow chip design cycles? Some of my earlier thoughts/tweet on the search space: Chip Design Is Basically a Massive Search Problem https://t.co/nO7yVME8Ng Retweeted by @jukan05 from @kevingubbi